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A29002/A290021 Series
256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Features
n 5.0V 10% for read and write operations n Access times: - 55/70/90/120/150 (max.) n Current: - 20 mA typical active read current - 30 mA typical program/erase current - 1 A typical CMOS standby n Flexible sector architecture - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector n Top or bottom boot block configurations available n Embedded Erase Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies bytes at specified addresses n Typical 100,000 program/erase cycles per sector n 20-year data retention at 125C - Reliable operation for the life of the system n Compatible with JEDEC-standards - Pinout and software compatible with single-powersupply Flash memory standard - Superior inadvertent write protection n Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations n Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation n Hardware reset pin ( RESET ) - Hardware method to reset the device to reading array data (not available on A290021) n Package options - 32-pin P-DIP, PLCC, or TSOP (Forward type)
General Description
The A29002 is a 5.0 volt-only Flash memory organized as 262,144 bytes of 8 bits each. The A29002 offers the RESET function, but it is not available on A290021. The 256 Kbytes of data are further divided into seven sectors for flexible sector erase capability. The 8 bits of data appear on I/O0 I/O7 while the addresses are input on A0 to A17. The A29002 is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29002 can also be programmed in standard EPROM programmers. The A29002 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29002 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29002 also offers the ability to program in the Erase Suspend mode. The standard A29002 offers access times of 55, 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29002 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin.
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The host system can detect whether a program or erase operation is complete by reading the I/O7 ( Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29002 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data (This feature is not available on the A290021).
Pin Configurations
n DIP
n PLCC
NC on A290021 RESET
NC on A290021
VCC
A12
A16
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
31 30 29
WE A17
4
3
A15
2
1
32
31
A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13
30
A17
WE
RESET
1
32
VCC
A29002/A290021
28 27 26 25 24 23 22 21 20 19 18 17
29 28 27
A14 A13 A8 A9 A11 OE A10 CE I/O7
A29002L/ A290021L
26 25 24 23 22 21
14
15
16
17
18
19 I/O5
VSS
I/O1
I/O2
I/O3
I/O4
I/O3
n TSOP (Forward type)
A11 A9 A8 A13 A14 A17 WE VCC RESET A16 NC on A290021 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
A29002V/A290021V
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I/O6
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Block Diagram
I/O0 - I/O7 VCC VSS
Erase Voltage Generator
Input/Output Buffers
WE RESET (N/A A290021)
State Control PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
Command Register
CE OE
Y-Decoder Address Latch STB VCC Detector Timer Y-Gating
X-decoder
Cell Matrix
A0-A17
Pin Descriptions
Pin No. A0 - A17 I/O0 - I/O7 Description Address Inputs Data Inputs/Outputs Chip Enable Write Enable Output Enable Hardware Reset (N/A A290021) Ground Power Supply
CE WE OE
RESET
VSS VCC
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Absolute Maximum Ratings*
Ambient Operating Temperature . . . . . -55C to + 125C Storage Temperature . . . . . . . . . . . . . . -65C to + 125C Ground to VCC . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V A9, OE & RESET (Note 2) . . . . . . . . . . . -2.0V to 12.5V All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC +0.5V. During voltage transitions, outputs may overshoot to VCC +2.0V for periods up to 20ns. 2. Minimum DC input voltage on A9 pins is -0.5V. During voltage transitions, A9, OE and RESET may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 and OE is +12.5V which may overshoot to 13.5V for periods up to 20ns. ( RESET is N/A on A290021) 3. No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second.
Operating Ranges
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . 0C to +70C VCC Supply Voltages VCC for 10% devices . . . . . . . . . . . . . . +4.5V to +5.5V Operating ranges define those limits between which the functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1. A29002/A290021 Device Bus Operations Operation Read Write CMOS Standby TTL Standby
CE
L L VCC 0.5 V H
OE
L H X X
WE
H L X X
RESET
(N/A A290021) H H VCC 0.5 V VCC 0.5 V H L VID
A0 - A17 AIN AIN X X
I/O0 - I/O7 DOUT DIN High-Z High-Z
Output Disable L H H X High-Z Reset X X X X High-Z Temporary Sector Unprotect (Note) X X X X X Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information. 2. This function is not available on A290021.
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Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH all the time during read operation. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms, lCC1 in the DC Characteristics table represents the active current specification for reading array data. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE & RESET pins ( CE only on A290021) are both held at VCC 0.5V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE is held at VIH, while RESET (Not available on A290021) is held at VCC0.5V. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics tables represents the standby current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to VIL, and OE to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.
RESET : Hardware Reset Pin (N/A on A290021)
The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET parameters and diagram.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on I/O7 - I/O0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams.
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Table 2. A29002/A290021 Top Boot Block Sector Address Table
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 A17 0 0 1 1 1 1 1 A16 0 1 0 1 1 1 1 A15 X X X 0 1 1 1 A14 X X X X 0 0 1 A13 X X X X 0 1 X Sector Size (Kbytes) 64 64 64 32 8 8 16 Address Range 00000h - 0FFFFh 10000h - 1FFFFh 20000h - 2FFFFh 30000h - 37FFFh 38000h - 39FFFh 3A000h - 3BFFFh 3C000h - 3FFFFh
Table 3. A29002/A290021 Bottom Boot Block Sector Address Table
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 A17 0 0 0 0 0 1 1 A16 0 0 0 0 1 0 1 A15 0 0 0 1 X X X A14 0 1 1 X X X X A13 X 0 1 X X X X Sector Size (Kbytes) 16 8 8 32 64 64 64 Address Range 00000h - 03FFFh 04000h - 05FFFh 06000h - 07FFFh 08000h - 0FFFFh 10000h - 1FFFFh 20000h - 2FFFFh 30000h - 3FFFFh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5V to 12.5 V) on address pinA9. Address pins A6, A1, and AO must be as shown in Autoselect
Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O7 - I/O0.To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode.
Table 4. A29002/A290021 Autoselect Codes (High Voltage Method)
Description Manufacturer ID: AMIC Device ID: A29002/ A290021 Sector Protection Verification Continuation ID A17 - A13 A12 - A10 X X Sector Address X X X A9 VID VID A8 - A7 X X A6 VIL VIL A5 - A2 X X A1 VIL VIL AO VIL VIH Identifier Code on I/O7 - I/O0 37h Top Boot Block: 8Ch Bottom Boot Block: 0Dh 01h (protected) 00h (unprotected) X VID X VIL X VIH VIH 7Fh
X
VID
X
VIL
X
VIH
VIL
Note: CE =VIL, OE =VIL and WE =VIH when Autoselect Mode
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Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details.
START
RESET = VID (Note 1)
Hardware Data Protection
The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array.
Perform Erase or Program Operations
RESET = VIH
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE , CE or WE do not initiate a write cycle.
Temporary Sector Unprotect Completed (Note 2)
Logical Inhibit
Write cycles are inhibited by holding any one of OE =VIL, CE = VIH or WE = VIH. To initiate a write cycle, CE and
Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again.
WE must be a logical zero while OE is a logical one.
Figure 1. Temporary Sector Unprotect Operation
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the device does not accept commands on the rising edge of WE . The internal state machine is automatically reset to reading array data on the initial power-up.
Temporary Sector Unprotect (N/A on A290021)
This feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram shows the timing waveforms, for this feature.
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Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX11h retrieves the continuation code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions table shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using I/O7 or I/O6. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1 ". Attempting to do so may halt the operation and set I/O5 to "1", or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
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Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase timeout of 50s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50s, the system need not monitor I/O3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor I/O3 to determine if the sector erase timer has timed out. (See the " I/O3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. Refer to "Write Operation Status" for information on these status bits.
Verify Data ? No Yes
Increment Address
Last Address ?
Yes Programming Completed
Note : See the appropriate Command Definitions table for program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence.
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Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
START
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on I/O7 - I/O0. The system can use I/O7, or I/O6 and I/O2 together, to determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within nonsuspended sectors. The system can determine the status of the program operation using the I/O7 or I/O6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm in progress
No Data = FFh ?
Yes
Erasure Completed
Note : 1. See the appropriate Command Definitions table for erase command sequences. 2. See "I/O3 : Sector Erase Timer" for more information.
Figure 3. Erase Operation
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Table 5. A29002/A290021 Command Definitions
Bus Cycles (Notes 2 - 4) Cycles First Addr Data RA XXX 555 555 555 555 555 555 555 XXX XXX RD F0 AA AA AA AA AA AA AA B0 30 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 555 555 555 555 555 555 555 90 90 90 90 A0 80 80 X00 X01 X03 SA X02 PA 555 555 37 8C 0D 7F 00 01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 Second Addr Data Third Fourth Fifth Sixth
Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID Autoselect (Note 7) Device ID Top Bottom Continuation ID
Addr Data Addr Data Addr Data Addr Data
1 1 4 4 4
Sector Protect Verify 4 (Note 8) Program Chip Erase Sector Erase Erase Suspend (Note 9) Erase Resume (Note 10) 4 6 6 1 1
Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A13 select a unique sector. Note: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operation. 4. Address bits A17 - A12 are don't cares for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high (while the device is providing status data). 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. 10. The Erase Resume command is valid only during the Erase Suspend mode.
11. The time between each command cycle has to be less than 50s.
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Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, and I/O7, are provided in the A29002/A290021 to determine the status of a write operation. Table 6 and the following subsections describe the functions of these status bits. I/O7, I/O6 and I/O2 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
START
Read I/O7-I/O0 Address = VA
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on I/O7 the complement of the datum programmed to I/O7. This I/O7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to I/O7. The system must provide the program address to read valid status information on I/O7. If a program address falls within a protected sector, Data Polling on I/O7 is active for approximately 2s, then the device returns to reading array data. During the Embedded Erase algorithm, Data Polling produces a "0" on I/O7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data Polling produces a "1" on I/O7.This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on I/O7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on I/O7 is active for approximately 100s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects I/O7 has changed from the complement to true data, it can read valid data at I/O7 - I/O0 on the following read cycles. This is because I/O7 may change asynchronously with I/O0 - I/O6 while Output Enable ( OE ) is asserted low. The Data Polling Timings (During Embedded Algorithms) figure in the "AC Characteristics" section illustrates this. Table 6 shows the outputs for Data Polling on I/O7. Figure 4 shows the Data Polling algorithm.
Yes I/O7 = Data ?
No
No I/O5 = 1?
Yes Read I/O7 - I/O0 Address = VA
Yes I/O7 = Data ?
No
FAIL
PASS
Note : 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5.
Figure 4. Data Polling Algorithm
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I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O6 to toggle. (The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, I/O6 toggles for approximately 100s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O6 and I/O2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O6 toggles. When the device enters the Erase Suspend mode, I/O6 stops toggling. However, the system must also use I/O2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use I/O7 (see the subsection on " I/O7 : Data Polling"). If a program address falls within a protected sector, I/O6 toggles for approximately 2s after the program command sequence is written, then returns to reading array data. I/O6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O2 vs. I/O6 figure shows the differences between I/O2 and I/O6 in graphical form. See also the subsection on " I/O2: Toggle Bit II". bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O2 and I/O6. Figure 5 shows the toggle bit algorithm in flowchart form, and the section " I/O2: Toggle Bit II" explains the algorithm. See also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The I/O2 vs. I/O6 figure shows the differences between I/O2 and I/O6 in graphical form.
Reading Toggle Bits I/O6, I/O2
Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7 - I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O7 - I/O0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O5 is high (see the section on I/O5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O5 has not gone high. The system may continue to monitor the toggle bit and I/O5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5).
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The I/O5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But I/O2 cannot distinguish whether the sector is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status
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I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system may read I/O3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, I/O3 switches from "0" to "1." The system may ignore I/O3 if the system can guarantee that the time between additional sector erase commands will always be less than 50s. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on I/O7 ( Data Polling) or I/O6 (Toggle Bit 1) to ensure the device has accepted the command sequence, and then read I/O3. If I/O3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If I/O3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O3 prior to and following each subsequent sector erase command. If I/O3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for I/O3.
START
Read I/O7-I/O0
Read I/O7-I/O0
(Note 1)
Toggle Bit = Toggle ? Yes No
No
I/O5 = 1?
Yes Read I/O7 - I/O0 Twice
(Notes 1,2)
Toggle Bit = Toggle ?
No
Yes Program/Erase Operation Not Commplete, Write Reset Command
Program/Erase Operation Complete
Notes : 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as I/O5 changes to "1". See text.
Figure 5. Toggle Bit Algorithm
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Table 6. Write Operation Status
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspend Sector Erase-Suspend-Program Notes: 1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. I/O5 switches to "1" when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "I/O5: Exceeded Timing Limits" for more information. I/O7 (Note 1) I/O6 Toggle Toggle No toggle Data Toggle I/O5 (Note 2) 0 0 0 Data 0 N/A 1 N/A Data N/A I/O3 I/O2 (Note 1) No toggle Toggle Toggle Data N/A
I/O7
0 1 Data
I/O7
Maximum Negative Input Overshoot
20ns
+0.8V
20ns
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V 20ns 20ns
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DC Characteristics
TTL/NMOS Compatible Parameter Parameter Description Symbol ILI Input Load Current ILIT ILO ICC1 ICC2 ICC3 VIL VIH VID VOL VOH A9, OE &RESET Input Load Current Output Leakage Current VCC Active Read Current (Notes 1, 2) VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) VCC Standby Current (Note 2) Input Low Level Input High Level Voltage for Autoselect and Temporary Unprotect Sector Output Low Voltage Output High Voltage VCC = 5.25 V IOL = 12mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min Test Description VIN = VSS to VCC. VCC = VCC Max VCC = VCC Max, A9, OE & RESET=12.5V VOUT = VSS to VCC. VCC = VCC Max Min. Typ. Max. 1.0 100 1.0 20 30 0.4 -0.5 2.0 10.5 30 40 1.0 0.8 VCC+0.5 12.5 0.45 2.4 Unit A A A mA mA mA V V V V V
CE = VIL, OE = VIH CE = VIL, OE =VIH CE = VIH, RESET= VCC 0.5V
CMOS Compatible Parameter Parameter Description Symbol ILI Input Load Current ILIT ILO ICC1 ICC2 ICC3 VIL VIH VID VOL VOH1 VOH2 A9, OE & RESET Input Load Current Output Leakage Current VCC Active Read Current (Notes 1,2) VCC Active Program/Erase Current (Notes 2,3,4) VCC Standby Current (Notes 2, 5) Input Low Level Input High Level Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE & RESET= 12.5V VOUT = VSS to VCC, VCC = VCC Max Min. Typ. Max. 1.0 100 1.0 20 30 1 -0.5 0.7 x VCC VCC = 5.25 V IOL = 12.0 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A. VCC = VCC Min 10.5 0.85 x VCC VCC-0.4 30 40 5 0.8 VCC+0.3 12.5 0.45 Unit A A A mA mA A V V V V V V
CE = VIL, OE = VIH CE = VIL, OE = VIH CE = RESET = VCC 0.5 V
Notes for DC characteristics (both tables): 1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested. 5. For CMOS mode only, ICC3 = 20A max at extended temperatures (> +85C). 6. RESET is not available on A290021.
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AC Characteristics
Read Only Operations Parameter Symbols JEDEC tAVAV tAVQV Std tRC tACC Read Cycle Time (Note 2) Address to Output Delay Min. Description Test Setup -55 55 55 -70 70 70 Speed -90 90 90 -120 120 120 -150 150 150 ns ns Unit
CE = VIL OE = VIL OE = VIL
Max.
tELQV tGLQV
tCE tOE
Chip Enable to Output Delay Output Enable to Output Delay Read Output Enable Hold Time (Note 2)
Max. Max. Min. Min. Max.
55 30 0 10 18 18
70 30 0 10 20 20 0
90 35 0 10 20 20 0
120 50 0 10 30 30 0
150 55 0 10 35 35 0
ns ns ns ns ns ns ns
tOEH
Toggle and
Data Polling
tEHQZ tGHQZ tAXQX tDF tDF tOH Chip Enable to Output High Z (Notes 1,2) Output Enable to Output High Z (Notes 1,2) Output Hold Time from Addresses, CE or OE , Whichever Occurs First Min.
0
Notes: 1. Output driver disable time. 2. Not 100% tested.
Timing Waveforms for Read Only Operation (RESET =VIH on A29002)
tRC Addresses tACC CE tDF OE tOEH WE tCE tOE Addresses Stable
tOH High-Z
Output
High-Z
Output Valid
0V
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Hardware Reset (RESET ) (N/A on A290021)
Parameter JEDEC Std tREADY tREADY tRP tRH Description Test Setup Max Max Min Min All Speed Options 20 500 500 50 Unit s ns ns ns
RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) RESET Pulse Width RESET High Time Before Read (See Note)
Note: Not 100% tested.
RESET Timings
CE, OE tRH RESET
tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
~ ~
RESET
tRP
Temporary Sector Unprotect (N/A on A290021)
Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) Min Min All Speed Options 500 4 Unit ns s
RESET Setup Time for Temporary Sector Unprotect
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
12V 0 or 5V RESET CE tVIDR Program or Erase Command Sequence tVIDR
~ ~
0 or 5V
~ ~
WE
~ ~
tRSP
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AC Characteristics
Erase and Program Operations Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recover Time Before Write ( OE high to WE low) Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Write Pulse Width High Max. Byte Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Set Up Time (Note 1) Typ. Typ. Min. 50 7 1 50 30 35 40 25 45 30 Description -55 55 -70 70 Speed -90 90 0 45 45 0 0 0 0 0 45 20 50 50 50 50 50 50 -120 120 -150 150 ns ns ns ns ns ns ns ns ns ns ns s s sec s Unit
CE Setup Time CE Hold Time
Write Pulse Width
Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.
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Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
Addresses
555h
PA
~ ~
tWC
tAS
PA
PA
tAH CE tCH
OE tWP WE tCS tDS Data A0h tWPH tDH PD tWHWH1
~ ~
~ ~
~ ~
tGHWL
~~ ~~
Status
DOUT
tVCS VCC
Note : PA = program addrss, PD = program data, Dout is the true data at the program address.
~ ~
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Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
Addresses
2AAh
SA 555h for chip erase
~ ~
VA
tWC
tAS VA
tAH
CE
OE
tCH tWP
WE tCS tDS Data 55h
tWPH tDH 30h 10h for chip erase
~ ~
tWHWH2
~ ~
tGHWL
~~ ~~
In Progress
~ ~
Complete
tVCS VCC
Note : SA = Sector Address. VA = Valid Address for reading status data.
~ ~
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Timing Waveforms for Data Polling (During Embedded Algorithms)
tRC Addresses VA tACC CE tCH OE tOEH WE tOH High-Z I/O7 Complement Complement True Valid Data tDF tCE
~ ~
VA
VA
~ ~
~ ~
~ ~
tOE
~~ ~~
High-Z Status Data
~ ~
I/O0 - I/O6
Status Data
True
Valid Data
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle.
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Timing Waveforms for Toggle Bit (During Embedded Algorithms)
tRC Addresses VA tACC CE tCH tCE VA
~ ~
VA
VA
tOE
tOEH WE
tDF
tOH
I/O6 , I/O2
Valid Status (first read)
Valid Status (second read)
~ ~
~ ~
Valid Status (stop togging)
~ ~
OE
~~ ~~
Valid Status
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
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Timing Waveforms for I/O2 vs. I/O6
~ ~
~ ~
~ ~
~ ~
WE
Erase
Erase Suspend Read
Erase Suspend Program
Erase Suspend Read
Erase
~ ~
Erase Complete
Enter Embedded Erasing
Erase Suspend
Enter Erase Suspend Program
Erase Resume
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
I/O6
~ ~
~ ~
I/O2
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Statue" for more information.
AC Characteristics
Erase and Program Operations Alternate CE Controlled Writes Parameter Symbols JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. 30 20 35 20 40 25 45 30 Description -55 55 -70 70 Speed -90 90 0 45 45 0 0 0 0 45 20 7 1 50 20 50 20 50 50 50 50 -120 120 -150 150 ns ns ns ns ns ns ns ns ns ns s sec Unit
WE Setup Time WE Hold Time
Write Pulse Width Write Pulse Width High Byte Programming Operation (Note 2) Sector Erase Operation (Note 2)
Notes: 3. Not 100% tested. 4. See the "Erase and Programming Performance" section for more information.
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~ ~
~ ~
A29002/A290021 Series
Timing Waveforms for Alternate CE Controlled Write Operation (RESET =VIH on A29002)
PA for program SA for sector erase 555 for chip erase Data Polling
555 for program 2AA for erase
~ ~
Addresses tWC tWH WE tAS tAH
PA
OE tCP tCPH tWS tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2
CE
~ ~
~ ~
~ ~
tGHEL
~ ~
~ ~
I/O7
DOUT
Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note 3) Typ. (Note 1) 1 8 35 3.6 Max. (Note 2) 8 64 300 10.8 Unit sec sec s sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system-level overhead (Note 5)
Notes: 1. Typical program and erase times assume the following conditions: 25C, 5.0V VCC, 100,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 4.5V (4.75V for -55), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
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Latch-up Characteristics
Description Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET) Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. RESET N/A on A290021 Min. -1.0V -100 mA -1.0V Max. VCC+1.0V +100 mA 12.5V
TSOP Pin Capacitance
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN=0 VOUT=0 VIN=0 Typ. 6 8.5 7.5 Max. 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0MHz
PLCC and P-DIP Pin Capacitance
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN=0 VOUT=0 VPP=0 Typ. 4 8 8 Max. 6 12 12 Unit pF pF pF
Notes: 3. Sampled, not 100% tested. 4. Test conditions TA = 25C, f = 1.0MHz
Data Retention
Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
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Test Conditions
Test Specifications Test Condition Output Load Output Load Capacitance, CL(including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0 - 3.0 1.5 1.5 -55 All others 1 TTL gate 100 20 0.45 - 2.4 0.8, 2.0 0.8, 2.0 pF ns V V V Unit
Test Setup
5.0 V
2.7 K Device Under Test
CL
6.2 K
Diodes = IN3064 or Equivalent
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Ordering Information Top Boot Sector Flash
Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (A)
Part No.
Package
A29002T-55 A290021T-55 A29002TL-55 A290021TL-55 A29002TV-55 A290021TV-55 A29002T-70 A290021T-70 A29002TL-70 A290021TL-70 A29002TV-70 A290021TV-70 A29002T-90 A290021T-90 A29002TL-90 A290021TL-90 A29002TV-90 A290021TV-90 A29002T-120 A290021T-120 A29002TL-120 A290021TL-120 A29002TV-120 A290021TV-120 A29002T-150 A290021T-150 A29002TL-150 A290021TL-150 A29002TV-150 A290021TV-150 150 20 30 1 120 20 30 1 90 20 30 1 70 20 30 1 55 20 30 1
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
(February, 2002, Version 1.0)
28
AMIC Technology, Inc.
A29002/A290021 Series
Ordering Information (continued) Bottom Boot Sector Flash
Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (A)
Part No.
Package
A29002U-55 A290021U-55 A29002UL-55 A290021UL-55 A29002UV-55 A290021UV-55 A29002U-70 A290021U-70 A29002UL-70 A290021UL-70 A29002UV-70 A290021UV-70 A29002U-90 A290021U-90 A29002UL-90 A290021UL-90 A29002UV-90 A290021UV-90 A29002U-120 A290021U-120 A29002UL-120 A290021UL-120 A29002UV-120 A290021UV-120 A29002U-150 A290021U-150 A29002UL-150 A290021UL-150 A29002UV-150 A290021UV-150 150 20 30 1 120 20 30 1 90 20 30 1 70 20 30 1 55 20 30 1
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
32Pin DIP
32Pin PLCC
32Pin TSOP
(February, 2002, Version 1.0)
29
AMIC Technology, Inc.
A29002/A290021 Series
Package Information
P-DIP 32L Outline Dimensions unit: inches/mm
D 32 17
E
1
16 E1 C
A2
A
A1
Base Plane
L
Seating Plane B B1 e EA
Symbol A A1 A2 B B1 C D E E1 EA e L
Dimensions in inches Min 0.015 0.149 1.645 0.537 0.590 0.630 0.120 0 Nom 0.154 0.018 0.050 0.010 1.650 0.542 0.600 0.650 0.100 0.130 Max 0.210 0.159 1.655 0.547 0.610 0.670 0.140 15
Dimensions in mm Min 0.381 3.785 41.783 13.64 14.986 16.002 3.048 0 Nom 3.912 0.457 1.270 0.254 41.91 13.767 15.240 16.510 2.540 3.302 Max 5.334 4.039 42.037 13.894 15.494 17.018 3.556 15
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins.
(February, 2002, Version 1.0)
30
AMIC Technology, Inc.
A29002/A290021 Series
Package Information PLCC 32L Outline Dimension
HD D 13 5
unit: inches/mm
14
4
1 32
20
30
21
29
A2
A
HE
E
b1 GD y D
A1
e
b
GE
Dimensions in inches
Dimensions in mm Min 0.47 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 0 Nom 2.80 0.71 0.46 0.254 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 Max 3.40 2.93 0.81 0.54 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.075 10
Symbol
A A1 A2 b1 b C D E e GD GE HD HE L y
Min 0.0185 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0
Nom 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 -
Max 0.134 0.115 0.032 0.021 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.003 10
Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.
(February, 2002, Version 1.0)
31
AMIC Technology, Inc.
L
c
A29002/A290021 Series
Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
D
unit: inches/mm
e
A2
E
A1
c
L LE
HD Detail "A"
Detail "A"
y
D
S
b
Dimensions in inches Symbol A A1 A2 b c D E e HD L LE S y 0.779 0.016 0 Min 0.002 0.037 0.007 0.004 0.720 Nom 0.039 0.009 0.724 0.315 0.020 BSC 0.787 0.020 0.032 0.795 0.024 0.020 0.003 5 Max 0.047 0.006 0.041 0.011 0.008 0.728 0.319
Dimensions in mm Min 0.05 0.95 0.18 0.11 18.30 Nom 1.00 0.22 18.40 8.00 0.50 BSC 19.80 0.40 0 20.00 0.50 0.80 20.20 0.60 0.50 0.08 5 Max 1.20 0.15 1.05 0.27 0.20 18.50 8.10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.
(February, 2002, Version 1.0)
32
AMIC Technology, Inc.
A

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